A DC/DC converter supplies a power-supply voltage to a digital-signal processing LSI such as an image-processing engine or a CPU. The DC/DC converter is required to have high load responsiveness for a dynamically fluctuating digital load to minimize a fluctuation range of an output voltage. To meet this requirement concerning a digital load, a ripple control method has been proposed and used widely. In the ripple control method, the load responsiveness is improved by not having an error amplifier which is a main factor of a delay element.
In this ripple control, a valley voltage of an output voltage ripple is compared with a reference voltage, and when the valley voltage of the output voltage ripple falls below the reference voltage, a high-side MOSFET is turned on for a certain period of time to enable fast-response operation.
Next, operation of the ripple control including what is described in Japanese Patent Application Publication No. 2011-199973 is described with reference to a circuit diagram of a prior art shown in FIG. 1 and a timing chart shown in FIG. 2.
A triangular wave generator 101 is configured to generate a triangular wave signal which increases a second reference voltage Vref2 while a high-side MOSFET 5 is off and decreases the second reference voltage Vref2 while the high-side MOSFET 5 is on. An adder 103 is configured to generate the second reference voltage Vref2 by adding the triangular wave signal from the triangular wave generator 101 to a first reference voltage Vref1 and output the second reference voltage Vref2 to a non-inverting input terminal of a feedback comparator 2.
A feedback voltage Vfb obtained by dividing an output voltage Vo by feedback-voltage dividing resistances 10 and 11 is inputted to an inverting input terminal of the feedback comparator 2. When this feedback voltage Vfb falls below a ceiling voltage of the second reference voltage Vref2, the feedback comparator 2 outputs an ON-trigger signal to an ON-timer 3.
The ON-timer 3 is configured to receive the ON-trigger signal as input, and output a high-side MOS ON-length signal to a drive circuit 4, the signal being proportional to the output voltage and inversely proportional to the input voltage. The drive circuit 4 is configured to receive the high-side MOS ON-length signal as input, and turn on the high-side MOSFET 5.
Once an ON-duration set by the on-timer 3 ends, the high-side MOSFET 5 is turned off, and a low-side MOSFET 6 is turned on. Thereafter, when the output voltage Vo decreases to cause the feedback voltage Vfb to fall below the ceiling voltage of the second reference voltage Vref2, the low-side MOSFET 6 is turned off, and the high-side MOSFET 5 is turned on again.
By repeating such operation, an inductor current is controlled, thereby supplying energy to an output capacitor 8 and an output load 9.
However, the ripple control method described in Japanese Patent Application Publication No. 2011-199973 has the following drawback. Specifically, in the ripple control method, feedback control is performed by a comparison between the valley voltage of the output voltage ripple and the reference voltage. Thus, when the output voltage ripple changes according to a change in the input voltage, an average value of the output voltage also fluctuates. As a result, the line regulation characteristics are degraded.
The ripple control method is described in detail with reference to the timing chart shown in FIGS. 2A and 2B and to line regulation characteristics shown in FIG. 3. As shown in FIGS. 2A and 2B, a variation range ΔIL of an inductor current tends to be higher when the input voltage is high than when the input voltage is low. This variation range ΔIL is represented by Formula (1):ΔIL=Vo·Tsw·(1−Vo/Vi)/L  (1),
where Tsw denotes a switch cycle.
An output voltage ripple Vorip is generated when this variation range ΔIL flows to the output capacitor 8 and the output load 9. Assuming that the output load is sufficiently larger than the impedance of the output capacitor, the output voltage ripple Vorip is represented by Formula (2):ΔVorip=Vo·Tsw·(1−Vo/Vi)·(1/(2π·Fsw·Co))/L  (2).
Further, the output voltage Vo is a voltage obtained by superimposing a half of the output voltage ripple Vorip on a DC component Vo(DC) of the output voltage, and is represented by Formula (3):Vo=Vo(DC)+Vorip/2=Vo(DC)+Vo·Tsw·(1−Vo/Vi)·(1/(2π·Fsw·Co))/2L  (3).
As can be seen in Formula (3), the higher an input voltage Vi is, the larger an average value of the output voltage ripple in the second term becomes and accordingly the higher the output voltage Vo becomes. Thus, as shown in FIG. 3, the line regulator characteristics are degraded.